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this is information on a product in full production. september 2014 docid016505 rev 5 1/28 tda7498mv 100 w mono btl class-d audio amplifier datasheet - production data features ? 100 w output power at thd = 10% with r l = 6 ? and v cc = 36 v ? 80-w output power at thd = 10% with r l = 8 ? and v cc = 34 v ? wide-range single-supply operation (14 - 39 v) ? high efficiency ( ? = 90%) ? four selectable, fixed gain settings of nominally 25.6 db, 31.6 db, 35.1 db and 37.6 db ? differential inputs minimize common-mode noise ? standby and mute features ? short-circuit protection ? thermal overload protection ? externally synchronizable description the tda7498mv is a mono btl class-d audio amplifier with single power supply designed for home systems and active speaker applications. it comes in a 36-pin powersso package with exposed pad up (epu) to facilitate mounting a separate heatsink. powersso-36 with exposed pad up table 1. device summary order code temperature range package packaging root part number 1tr -40 to 85 c powersso-36 (epu) tape and reel www.st.com
contents tda7498mv 2/28 docid016505 rev 5 contents 1 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2.1 for r l = 6 ?? ????????????????????????????????????????????????????????????? ??????????????????????????????????????????? 4.2.2 for r l = 8 ?? ????????????????????????????????????????????????????????????? ??????????????????????????????????????????? 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3 gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4 input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.5 internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5.1 master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5.2 slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.6 output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.7 protection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.8 diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
docid016505 rev 5 3/28 tda7498mv list of tables 28 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 6. electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 7. mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8. gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. how to set up synclk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. powersso-36 exposed pad up dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
list of figures tda7498mv 4/28 docid016505 rev 5 list of figures figure 1. internal block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connections (top view, pcb view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4. output power (thd = 10%) vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. thd vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6. thd vs. frequency (1 w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. thd vs. frequency (100 mw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 8. frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 9. fft performance (0 dbfs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. fft performance (-60 dbfs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 11. output power (thd = 10%) vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 12. thd vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 13. thd vs. frequency (1 w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 14. thd vs. frequency (100 mw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 15. frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 16. fft performance (0 db) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 17. fft performance (-60 db) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 18. application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 19. standby and mute circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 20. turn-on/off sequence for minimizing speaker ?pop? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 21. input circuit and frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 22. master and slave connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 23. typical lc filter for an 8 ? speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 24. typical lc filter for a 6 ? speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 25. behavior of pin diag for various protection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 26. powersso-36 epu outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
docid016505 rev 5 5/28 tda7498mv device block diagram 28 1 device block diagram figure 1 shows the block diagram of the tda7498mv. figure 1. internal block diagram
pin description tda7498mv 6/28 docid016505 rev 5 2 pin description 2.1 pinout figure 2. pin connections (top view, pcb view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 32 33 34 35 36 19 20 21 22 23 24 25 26 27 vss sub_gnd n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. outn outn pvcc pvcc pgnd pgnd outp outp pgnd vddpw stby mute inp inn rosc synclk vdds sgnd diag svr gain0 gain1 vdds2 sgnd2 vref svcc ep, exposed pad connect to ground
docid016505 rev 5 7/28 tda7498mv pin description 28 2.2 pin list table 2. pin description list pin n name type description 1 sub_gnd pwr connect to the frame 2,3 n.c. - no internal connection 4,5 n.c. - no internal connection 6,7 n.c. - no internal connection 8,9 n.c. - no internal connection 10,11 outn o negative pwm output for audio channel 12,13 pvcc pwr power supply for audio channel 14,15 pgnd pwr power stage ground 16,17 outp o positive pwm output for audio channel 18 pgnd pwr power stage ground 19 vddpw o 3.3-v (nominal) regulator output referred to ground for power stage 20 stby i standby mode control 21 mute i mute mode control 22 inp i positive differential input 23 inn i negative differential input 24 rosc o master oscillator frequency-setting pin 25 synclk i/o clock in/out for external oscillator 26 vdds o 3.3-v (nominal) regulator output referred to ground for signal blocks 27 sgnd pwr signal ground 28 diag o open-drain diagnostic output 29 svr o supply voltage rejection 30 gain0 i gain setting input 1 31 gain1 i gain setting input 2 32 vdds2 o connect to vdds (pin 26) 33 sgnd2 pwr connect to sgnd (pin 27) 34 vref o half vdds (nominal) referred to ground 35 svcc pwr signal power supply decoupling 36 vss o 3.3-v (nominal) regulator output referred to power supply - ep - exposed pad for heatsink, to be connected to ground
electrical specifications tda7498mv 8/28 docid016505 rev 5 3 electrical specifications 3.1 absolute maximum ratings warning: stresses beyond those listed under ?absolute maximum ratings? make cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating condition? are not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. in the real application, power supply with nominal value rated inside recommended operating conditions may experience some rising beyond the maximum operating condition for short time when no or very low current is sunk (amplifier in mute state). in this case the reliability of the device is guaranteed, provided that the absolute maximum rating is not exceeded. 3.2 thermal data 3.3 recommended operating conditions table 3. absolute maximum ratings symbol parameter value unit v cc_max dc supply voltage for pins pvcca, pvccb 44 v v l_max voltage limits for input pins stby, mute, inna, inpa, innb, inpb, gain0, gain1 -0.3 to 3.6 v t j_max operating junction temperature 0 to 150 c t op_max operating temperature -40 to 85 c t stg storage temperature -40 to 150 c table 4. thermal data symbol parameter min typ max unit r th j-case thermal resistance, junction to case - 2 3 c/w table 5. recommended operating conditions symbol parameter min typ max unit v cc supply voltage for pins pvcca, pvccb 14 - 39 v t amb ambient operating temperature -20 - 85 c
docid016505 rev 5 9/28 tda7498mv electrical specifications 28 3.4 electrical specifications unless otherwise stated, the results in table 6 below are given for the conditions: v cc = 36 v, r l (load) = 6 ? , r osc = r3 = 39 k ? , c8 = 100 nf, f = 1 khz, g v = 25.6 db and t amb = 25 c. table 6. electrical specifications symbol parameter condition min typ max unit i q total quiescent current no lc filter, no load - 40 60 ma i qstby quiescent current in standby - - 1 10 a v os output offset voltage play mode -100 - 100 mv mute mode -60 - 60 i ocp overcurrent protection threshold r l = 0 ? 5.5 7 - a t js junction temperature at thermal shutdown - - 150 - c r i input resistance differential input 48 60 - k ? v ovp overvoltage protection threshold - 42 43 - v v uvp undervoltage protection threshold - --8v r dson power transistor on resistance high side - 0.2 - ? low side - 0.2 - p o output power thd = 10% - 100 - w thd = 1% - 78 - p o output power r l = 8 ? , thd = 10%, v cc = 36v -80-w p d dissipated power p o = 100 w, thd = 10% -10-w ? efficiency p o = 100 w - 90 - % thd total harmonic distortion p o = 1 w - 0.1 - % g v closed-loop gain gain0 = l, gain1 = l 24.6 25.6 26.6 db gain0 = l, gain1 = h 30.6 31.6 32.6 gain0 = h, gain1 = l 34.1 35.1 36.1 gain0 = h, gain1 = h 36.6 37.6 38.6 ? g v gain matching - -1 - 1 db en total input noise a curve, g v = 20 db - 15 - v f = 22 hz to 22 khz - 25 50 svrr supply voltage rejection ratio fr = 100 hz, vr = 0.5 vpp, c svr = 10 f -70-db t r , t f rise and fall times - - 50 - ns f sw switching frequency internal oscillator 290 310 330 khz
electrical specifications tda7498mv 10/28 docid016505 rev 5 f swr output switching frequency range with internal oscillator (1) 250 - 400 khz with external oscillator (2) 250 - 400 v inh digital input high (h) - 2.3 - - v v inl digital input low (l) - - 0.8 v stby pin stby voltage high (h) - 2.9 - - v pin stby voltage low (l) - - 0.5 v mute pin mute voltage high (h) - 2.5 - - v pin mute voltage low (l) - - 0.8 a mute mute attenuation v mute < 0.8 v - 70 - db 1. f sw = 10 6 / ((16 * r osc + 182) * 4) khz, f synclk = 2 * f sw with r3 = 39 k ? (see figure 18. ). 2. f sw = f synclk / 2 with the external oscillator. table 6. electrical specifications (continued) symbol parameter condition min typ max unit
docid016505 rev 5 11/28 tda7498mv characterization curves 28 4 characterization curves figure 18 on page 18 shows the test circuit with which the characterization curves, shown in the next sections, were measured. figure 3 shows the pcb layout. 4.1 test board figure 3. test board r e p p o c p o t w e i v p o t r e p p o c m o t t o b w e i v m o t t o b
characterization curves tda7498mv 12/28 docid016505 rev 5 4.2 characterization curves unless otherwise stated, the measurements were made under the following conditions: v cc = 36 v, f = 1 khz, g v = 25.6 db, r osc = 39 k ? , c osc = 100 nf, t amb = 25 c. 4.2.1 for r l = 6 ? figure 4. output power (thd = 10%) vs. supply voltage figure 5. thd vs. output power 10 120 20 30 40 50 60 70 80 90 100 110 output power (w) +10 +36 +12 +14 +16 +18 +20 +22 +24 +26 +28 +30 +32 +34 supply voltage (v) 0.005 10 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 thd+n (%) 100m 200 200m 500m 1 2 5 10 20 50 100 output power (w) f = 1 khz f = 100 hz
docid016505 rev 5 13/28 tda7498mv characterization curves 28 figure 6. thd vs. frequency (1 w) figure 7. thd vs. frequency (100 mw) figure 8. frequency response thd+n (%) 20 20k 50 100 200 500 1k 2k 5k 10k frequency (hz) 0.01 2 0.02 0.05 0.1 0.2 0.5 1 0.01 2 0.02 0.05 0.1 0.2 0.5 1 thd+n (%) 20 20k 50 100 200 500 1k 2k 5k 10k frequency (hz) -3 +3 -2.5 -2 -1.5 -1 -0.5 +0 +0.5 +1 +1.5 +2 +2.5 ampl (db) 10 20k 20 50 100 200 500 1k 2k 5k 10k frequency (hz)
characterization curves tda7498mv 14/28 docid016505 rev 5 figure 9. fft performance (0 dbfs) figure 10. fft performance (-60 dbfs) fft (db) 20 20k 50 100 200 500 1k 2k 5k 10k frequency (hz) -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 fft (db) 20 20k 50 100 200 500 1k 2k 5k 10k frequency (hz) -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
docid016505 rev 5 15/28 tda7498mv characterization curves 28 4.2.2 for r l = 8 ? figure 11. output power (thd = 10%) vs. supply voltage figure 12. thd vs. output power 10 120 20 30 40 50 60 70 80 90 100 110 output power (w) +10 +36 +12 +14 +16 +18 +20 +22 +24 +26 +28 +30 +32 +34 supply voltage (v) 0.005 10 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 thd+n (%) 100m 200 200m 500m 1 2 5 10 20 50 100 output power (w) f = 1 khz f = 100 hz
characterization curves tda7498mv 16/28 docid016505 rev 5 figure 13. thd vs. frequency (1 w) figure 14. thd vs. frequency (100 mw) figure 15. frequency response thd+n (%) 20 20k 50 100 200 500 1k 2k 5k 10k frequency (hz) 0.01 2 0.02 0.05 0.1 0.2 0.5 1 thd+n (%) 20 20k 50 100 200 500 1k 2k 5k 10k frequency (hz) 0.01 2 0.02 0.05 0.1 0.2 0.5 1 -3 +3 -2.5 -2 -1.5 -1 -0.5 +0 +0.5 +1 +1.5 +2 +2.5 ampl (db) 10 20k 20 50 100 200 500 1k 2k 5k 10k frequency (hz)
docid016505 rev 5 17/28 tda7498mv characterization curves 28 figure 16. fft performance (0 db) figure 17. fft performance (-60 db)

fft (db) 20 20k 50 100 200 500 1k 2k 5k 10k frequency (hz) -180 +0 -170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
tda7498mv application information docid016505 rev 5 18/28 5 application information 5.1 application circuit figure 18. application circuit vcc gnd out-1 out-2 tda74 9 8mv mute stby 3v3 power supply single-ended * * input class-d amplifier * * load = 6 ohm for frequency shift output input * lc filter components load l1,l2 c26 c24,c28 6 ohm 8 ohm 22 h 22 h 470 nf 680 nf 220 nf 220 nf c5 100nf r3 3 9 k l4 22h c1 1f c2 1f c8 100nf c25 100nf c27 330pf r6 22r c40 220nf c41 220nf r1 100k r7 22r c6 100nf r4 120k r2 33k c26 680nf c10 100nf j6 j5 2 1 3 s1 2 1 3 s2 c2 9 2.2f 2 gnd 1 out 3 in ic2 l4 9 31cz33 1 2 j2 j7 + c23 2200f 50v l3 22h j4 c30 1f r14 100k r15 8r c28 220nf r16 8r c24 220nf r13 47k + c7 2.2f 16v d1 18v c 9 100nf c4 1nf c3 1nf c16 10f 10v c17 10f 10v r 9 180k 1 2 3 q1 ktc3875(s) 32 vdds2 36 vss 9 nc 5 nc 7 nc 3 nc 10 outn 12 pvcc 14 pgnd 16 outp 33 sgnd2 8 nc 4 nc 21 mute 6 nc 2 nc 2 9 svr 11 outn 1 sub_gnd 22 inp 23 inn 27 sgnd 26 vdds 28 diag 1 9 vddpw 18 pgnd 20 stby 24 rosc 31 gain1 35 svcc 30 gain0 25 synclk 17 outp 15 pgnd 34 vref 13 pvcc ic3 tda74 9 8mv j3 1 2 j 9 r8 6.8k + c15 2.2f 16v diag 3v3 fs fs vdds vdds vdds vcc 3v3
docid016505 rev 5 19/28 tda7498mv application information 28 5.2 mode selection the three operating modes of the tda7498mv are set by the two inputs, stby (pin 20) and mute (pin 21). ? standby mode: all circuits are turned off, very low current consumption. ? mute mode: inputs are connected to ground and the positive and negative pwm outputs are at 50% duty cycle. ? play mode: the amplifiers are active. the protection functions of the tda7498mv are realized by pulling down the voltages of the stby and mute inputs shown in figure 19 . the input current of the corresponding pins must be limited to 200 a. figure 19. standby and mute circuits figure 20. turn-on/off sequence for minimizing speaker ?pop? table 7. mode settings mode stby mute standby l (1) 1. drive levels defined in table 6: electrical specifications on page 9 x (don?t care) mute h (1) l play h h stby mute 0 v 3.3 v c7 2.2 f r2 30 k ? standby 0 v 3.3 v c15 2.2 f r4 30 k ? mute root part vcc stby mute input output i q standby mute play mute standby t t t t t t 0 0 0 0 0 0
application information tda7498mv 20/28 docid016505 rev 5 5.3 gain setting the gain of the tda7498mv is set by the two inputs, gain0 (pin 30) and gain1 (pin31). internally, the gain is set by changing the feedback resistors of the amplifier. 5.4 input resistance and capacitance the input impedance is set by an internal resistor ri = 60 k ? (typical). an input capacitor (ci) is required to couple the ac input signal. the equivalent circuit and frequency response of the input components are shown in figure 21 . for ci = 470 nf the high-pass filter cut-off frequency is below 20 hz: f c = 1 / (2 * ? * ri * ci) figure 21. input circuit and frequency response table 8. gain settings gain0 gain1 nominal gain, g v (db) l l 25.6 l h 31.6 h l 35.6 h h 37.6 ri input ci rf input pin signal
docid016505 rev 5 21/28 tda7498mv application information 28 5.5 internal and external clocks the clock of the class-d amplifier can be generated internally or can be driven by an external source. if two or more class-d amplifiers are used in the same system, it is recommended that all devices operate at the same clock frequency. this can be implemented by using one tda7498mv as master clock, while the other devices are in slave mode, that is, externally clocked. the clock interconnect is via pin synclk of each device. as explained below, synclk is an output in master mode and an input in slave mode. 5.5.1 master mode (internal clock) using the internal oscillator, the output switching frequency, f sw , is controlled by the resistor, r osc , connected to pin rosc: f sw = 10 6 / ((r osc * 16 + 182 ) * 4) khz where r osc is in k ? . in master mode, pin synclk is used as a clock output pin whose frequency is: f synclk = 2 * f sw for master mode to operate correctly then resistor r osc must be less than 60 k ? as given below in table 9 . 5.5.2 slave mode (external clock) in order to accept an external clock input the pin rosc must be left open, that is, floating. this forces pin synclk to be internally configured as an input as given in table 9 . the output switching frequency of the slave devices is: f sw = f synclk / 2 figure 22. master and slave connection table 9. how to set up synclk mode rosc synclk master r osc < 60 k ? output slave floating (not connected) input synclk rosc rosc cosc rosc synclk 39 k ? 100 nf output input master slave root part root part
application information tda7498mv 22/28 docid016505 rev 5 5.6 output low-pass filter to avoid emi problems, it may be necessary to use a low-pass filter before the speaker. the cut-off frequency should be larger than 22 khz and much lower than the output switching frequency. it is necessary to choose the l and c component values depending on the loudspeaker impedance. some typical values, which give a cut-off frequency of 27 khz, are shown in figure 23 and figure 24 below. figure 23. typical lc filter for an 8 ? speaker figure 24. typical lc filter for a 6 ? speaker ( u ( u & p m h o & n m h o & n m h o & n & n & n m h o 0 ? - 7 0 . ? - 7 0 ( u ( u & p m h o & n m h o & n m h o & n & n & n m h o 0 ? - 7 0 . ? - 7 0
docid016505 rev 5 23/28 tda7498mv application information 28 5.7 protection function the tda7498mv is fully protected against overvoltage, undervoltage, overcurrent and thermal overloads as explained here. overvoltage protection (ovp) if the supply voltage exceeds the value for v ovp given in table 6: electrical specifications on page 9 the overvoltage protection is activated which forces the outputs to the high-impedance state. when the supply voltage falls back to within the operating range the device restarts. undervoltage protection (uvp) if the supply voltage drops below the value for v uvp given in table 6: electrical specifications on page 9 the undervoltage protection is activated which forces the outputs to the high-impedance state. when the supply voltage recovers to within the operating range the device restarts. overcurrent protection (ocp) if the output current exceeds the value for i ocp given in table 6: electrical specifications on page 9 the overcurrent protection is activated which forces the outputs to the high-impedance state. periodically, the device attempts to restart. if the overcurrent condition is still present then the ocp remains active. the restart time, t oc , is determined by the r-c components connected to pin stby. thermal protection (otp) if the junction temperature, t j , reaches 145 c (nominally), the device goes to mute mode and the positive and negative pwm outputs are forced to 50% duty cycle. if the junction temperature reaches the value for t j given in table 6: electrical specifications on page 9 the device shuts down and the output is forced to the high-impedance state. when the device cools sufficiently the device restarts. 5.8 diagnostic output the output pin diag is an open drain transistor. when any protection is activated it switches to the high-impedance state. the pin can be connected to a power supply (< 39 v) by a pull- up resistor whose value is limited by the maximum sinking current (200 a) of the pin. figure 25. behavior of pin diag for various protection conditions root part protection logic r1 diag vdd vdd overcurrent protection restart restart ov, uv, ot protection
package mechanical data tda7498mv 24/28 docid016505 rev 5 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. the tda7498mv comes in a 36-pin powersso package with exposed pad up (epu). figure 26 shows the package outline and table 10 gives the dimensions.
tda7498mv package mechanical data docid016505 rev 5 25/28 figure 26. powersso-36 epu outline drawing 7618147_f
package mechanical data tda7498mv 26/28 docid016505 rev 5 table 10. powersso-36 exposed pad up dimensions symbol dimensions in mm. dimensions in inch. min. typ. max. min. typ. max. a 2.15 - 2.45 0.085 - 0.096 a2 2.15 - 2.35 0.085 - 0.092 a1 0 - 0.1 0.00 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 d 10.10 - 10.50 0.398 - 0.413 e 7.4 - 7.6 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - f - 2.3 - - 0.091 - g - - 0.1 - - 0.004 h 10.1 - 10.5 - - 0.413 h - - 0.4 - - 0.016 k 0 deg - 8 deg 0 deg - 8 deg l 0.55 - 0.85 0.022 0.033 m - 4.3 - - 0.169 - n - - 10 deg - - 10 deg o - 1.2 - - 0.047 - q - 0.8 - - 0.031 - s - 2.9 - - 0.114 - t - 3.65 - - 0.114 - u - 1.0 - - 0.039 -
docid016505 rev 5 27/28 tda7498mv revision history 28 7 revision history table 11. document revision history date revision changes 30-nov-2009 1 initial release. 28-jul-2010 2 removed datasheet preliminary status, updated features list and updated device summary table on page 1 added operating temperature range to table 3 on page 8 updated minimum supply voltage and temperature range in table 5: recommended operating conditions on page 8 updated voltage for logical 1 on pin stby in table 6 on page 9 27-jan-2011 3 updated applications circuit in figure 18 on page 18 . 24-feb-2014 4 updated order code table 1 on page 1 19-sep-2014 5 updated figure 2: pin connections (top view, pcb view) updated package information (representation on page 1, figure 26 , table 10 )
tda7498mv 28/28 docid016505 rev 5 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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